1. Field of the Invention
The invention relates in general to a semiconductor memory device. More particularly, this invention relates a redundant circuit for a semiconductor memory device that effectively avoids the generation of an interference signal in a dynamic precharge logic.
2. Description of the Related Art
While fabricating a semiconductor memory device such as a dynamic random access memory (DRAM) or a synchronous dynamic random access memory (SDRAM), a high yield is demanded. When a semiconductor memory device includes several defect memory cells, or even when only one defect memory cell exists, the memory device is a failed product. For a device with a high integration, the possibility of containing more defect memory cells is much higher than that with a low integration. As a consequence, the yield is decreased with increasing the integration.
As the fabrication process of semiconductor memory devices becomes more and more advanced, the packaging density becomes more and more complex and the technique thereof is more and more difficult. During the fabrication process, the existence of contamination or particles is inevitable, so that the yield is reduced. In the conventional technique, a method of fabricating a redundant circuit to result in a required yield is employed. The technique provides a redundant circuit in addition to the memory array for storing binary data, so as to substitute the defect memory cells. Each redundant memory cell is coupled to a word line and a bit line respectively. If memory array are found to be faulty, the redundant memory cells are to replace the position of these defect memory cells. Therefore, a defect-less memory chip is fabricated.
In other words, in addition to a main memory array, a backup memory array (or a redundant memory array) is formed to replace those defect memory cells in the main memory array. The memory device with both the main memory array which contains defect memory cells and the redundant memory array can be operated as a defect-less memory device.
The redundant memory array is typically formed in a periphery of the main memory array. The redundant memory array is very often connected with the main memory array via a fuse. The fuse may be blown by a laser light beam or a current flow. While repairing defect memory cells, the fuse can be open by applying a current or a laser light beam. The fuse remains close while the repairing step is not performed.
In the design of a DRAM, the dynamic precharge logic circuit can be used to design a redundant circuit. The processing speed of this kind of redundant circuit is much faster than that of the static gate.
Moreover, in the design of a high speed memory device, the pulse width may be across two clock cycle times. That is, when the clock signal CLK is raised to a high potential level, the bit-switch control signal may still remain in a high potential level. Thus, the interference signal generated by a precharge dynamic circuit may enable two or more than two bit-switch control signals simultaneously.
FIG. 1 shows a circuit diagram of a conventional redundant circuit. The redundant includes a PMOS transistor 10, a fuse 12 and inverters 14 and 16. The source of the PMOS transistor 10 is coupled to a voltage supply VCC, the gate of the PMOS transistor 10 is receive a precharge signal npre, the drain of the PMOS transistor is coupled to the fuse 12. The fuse 12 has a grounded terminal and a terminal coupled to an address signal CA. The inverter 14 has an input terminal coupled to the drain of the PMOS transistor 10, and an output terminal coupled to an input terminal of the inverter 16. The inverter 16 outputs an output bit-switch control signal rbsc.
Referring to both FIG. 1 and FIG. 2, waveforms of signals such as the clock signal CLK, address signal CA, precharge signal npre, node A, node B and the conventional bit-switch control signal rbsc of various potential levels are illustrated. When the clock signal CLK raises up to a high potential level (High), the precharge signal npre becomes at a low potential level (Low). Meanwhile, the PMOS transistor 10 is turned on to precharge the node A up to the voltage level of the voltage supply VCC. If the column address signal CA is matched with the repaired address, the fuse 12 is open. At the moment, the node A is at a high level, and the node B is at a low level, while the bit-switch control signal rbsc is maintained at a high level. In contrast, if the column address signal CA is not matched with the repaired address, the fuse 12 is remained close. Therefore, a path is established from node A to ground, so that the node A is switched to a low level.
However, as mentioned above, the pulse width of the bit-switch control signal can be across two clock cycle times. That is, when the clock signal CLK raises to a high level, the bit-switch control signal may still remain in a high level as shown as the waveform of bsc. Thus, at the precharge node A, an interference signal 52 may be generated which may destroy the data shown in a bit line sense amplifier. For outputting the normal bit-switch control signal bsc, it is obvious that the bit-switch control signal bsc may generate an interference signal 52.